Compression and decompression of stimulus and response waveforms in automated test systems

ABSTRACT

An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus waveform data are decompressed, and if required converted to analog form, then applied as a stimulus to the DUT. In response, the DUT produces a response waveform. The response waveform is compressed before transferring it to a storage device or over a data transfer interface. If the response waveform is analog, it is converted to digital before compression. The compressed waveform is decompressed for further analysis or display by a host computer. Features of the response waveform can be calculated from the compressed or uncompressed waveform data. Several configurations that include compression and decompression of stimulus and/or response waveforms in test systems are described.

This application is a continuation of application Ser. No. 11/776,359filed on 11 Jul. 2007, which application claims the benefit of U.S.Provisional Application No. 60/872,430 filed on 28 Nov. 2008.

BACKGROUND OF THE INVENTION

This invention relates to the generation, compression and decompressionof stimulus waveforms and the capture, compression and decompression ofresponse waveforms in automated test and measurement systems, especiallysystems that accept and/or generate electrical and/or optical signals.

In commonly owned U.S. Pat. No. 7,071,852 B1 (“the '852 patent”),entitled “Enhanced Test and Measurement Instruments Using Compressionand Decompression,” dated Jul. 4, 2006 and herein incorporated byreference, the present inventor discloses compression and decompressionmethods for test and measurement instruments, including arbitrarywaveform generators (AWG) and digital storage oscilloscopes (DSO). Inthe commonly owned and copending U.S. patent application Ser. No.11/458,771 (the '771 application) entitled, “Enhanced Time-InterleavedA/D Conversion Using Compression,” filed on Jul. 20, 2006 and hereinincorporated by reference, the present inventor describes compression ofa bandlimited signal that is sampled by a parallel time-interleavedanalog-to-digital converter (TIADC). The compression methods describedtherein are designed to take advantage of the parallel architecture ofthe TIADC. The compression methods of the '771 application can beimplemented in a test and measurement system that includes a TIADC. Inthe commonly owned and copending U.S. patent application Ser. No.11/553,147 (the '147 application), entitled “Data Compression for aWaveform Data Analyzer”, filed on 26 Oct. 2006 and herein incorporatedby reference, the present inventor describes compression of waveformhaving recurring waveform states and teaches algorithms for thisparticular type of waveform.

It is a well known practice in the art to test electronic devices byapplying a digital or an analog stimulus to the input of a system undertest (SUT), device under test (DUT) or a circuit under test (CUT) and toanalyze the response to determine proper operation. Using thismethodology, automatic test equipment (ATE) systems test billions ofintegrated circuits (ICs), or “chips,” each year, including mixed-signaland system-on-chip (SoC) devices. The stimulus and response methodologyis used to test individual integrated circuits, printed circuit boards,systems, electronic products and the like. Regardless of the item beingtested, the methodology of applying a stimulus to a SUT, DUT or CUT andobserving the response is common practice in the test and measurementfield. Depending on the system or device being tested, the stimulus andresponse signals can be electrical or optical. Because of the commonstimulus and response methodology, the terms SUT, DUT and CUT are usedinterchangeably in the following discussion and are not intended tolimit the scope to testing any particular circuit, device or system.

A desirable goal of automated test systems is to test a SUT as quicklyas possible. Mixed-signal devices and SoC devices are increasingly usedin high-volume, low-cost consumer electronics, such as in mobile phones,digital cameras and digital music players. As the prevalence ofmixed-signal and SoC devices increases, so does the importance oftesting these devices in an efficient, cost-effective manner.

Many SUTs have an analog input or an analog output. Testing these SUTscan require converting digital waveform samples to a correspondinganalog stimulus waveform prior to stimulating the device or convertingan analog response waveform from the device to a corresponding digitalform. For this reason, many ATE systems include analog-to-digitalconverters (ADC) and digital-to-analog converters (DAC).

In many ATE systems, both stimulus and response signals are created,stored and manipulated in digital form. Stimulus signals are oftenstored in digital form in at least one stimulus memory. Storing stimuluswaveforms provides flexibility to the testing process because thestimulus waveform can easily be created, retrieved, copied, moved,repeated, or reordered before being applied to the SUT. Similarly,response waveforms are often captured in digital form in at least onecapture memory. When response waveforms are captured in digital form,they can easily be retrieved, measured, copied and transferred from oneATE subsystem to another.

It is common practice to implement stimulus and response memories usingdynamic random access memory (DRAM) integrated circuits or DRAM modules,or using static random access memory (SRAM), or using flash memory (NORor NAND flash). Stimulus and response memories can also be implementedusing rotating media such as magnetic disk drives, CD-ROM drives,optical drives, DVD drives, and the like. The memory described hereinapplies to any form of data storage and is not limited to any particularphysical implementation.

Stimulus and response memories can create bottlenecks in an ATE systembecause they have both limited capacity and limited access bandwidth. Inparticular, stimulus memory becomes a bottleneck when it cannot storeall stimulus waveforms for a particular test or it cannot be accessedfast enough to accommodate the input data rate of the SUT. Similarly,response memory becomes a bottleneck when its access rate is too slow orits capacity is insufficient to capture the response waveform data fromthe SUT.

Other bottlenecks can arise as a result of the architecture of the ATEsystem. In many ATE systems the SUT is attached to one part of the testsystem called the “test head” and the overall control of the ATE systemis performed by a controlling computer. Often, the controlling computeris the original source of stimulus waveforms and the ultimatedestination of response waveforms. The limited bandwidth of theconnection between the test head and the SUT limits the data transferrate, creating an additional bottleneck. In the following discussion, an“instrument” refers to a printed circuit board or card in the test head.

In some ATE systems, the stimulus waveforms are generated by one or morearbitrary waveform generators (AWG) in the test head. An AWG generatesan analog stimulus waveform by reading waveform samples from a memoryand using a DAC to convert the samples to an analog stimulus waveform.The test head can also include one or more digitizers for capturing ananalog response waveform. A digitizer converts the analog responsewaveform using an ADC and stores the response waveform samples in amemory.

The test head may include other instruments to generate digital stimuluspatterns that are applied directly to the serial or parallel inputs ofthe DUT. For example, when testing a DAC, the ATE provides the digitalstimulus waveform, such as DC levels, ramps, sawtooths, sine waves,etc., directly to the serial or parallel inputs of the DAC. The analogoutput of the DAC under test is captured by a digitizer and sampled asdescribed above. Other response capture instruments in the test head cancapture digital response waveforms directly from the DUT. For example,when testing an ADC, the ATE provides an analog stimulus waveform to theADC. The ADC samples the analog stimulus waveform to provide digitalresponse waveform samples on its serial or parallel outputs. The ATEresponse capture instrument stores the samples in a capture memory.

Emerging technologies in the field of IC test and measurement includebuilt-in self test (BIST), design-for-manufacturability (DFM) anddesign-for-test (DFT). These emerging technologies address the problemsof testing ICs with increasing complexity and on-chip clock ratessubstantially higher than chip interface rates by including stimulusgenerators and response capture circuitry within the IC itself. In BISTarchitectures, testing cores are integrated with the system to be testedto mitigate the limitations of the chip interface. The present inventionis suitable for integration as an enhancement for stimulus generation,response capture, or both, and thus improves existing BIST, DFM, and DFTpractices.

FIG. 1 is a block diagram showing an example of a typical test systemfrom the prior art. A SUT 200 is stimulated with an analog stimuluswaveform 190 or a digital stimulus waveform 160. The SUT 200 produces ananalog response 220 and/or a digital response 210 that are captured forfurther processing. The host processor 100 coordinates the variousoperations required to perform the test. The host processor 100 can haveany architecture appropriate for the test system, including mainframe,personal computer (PC), card-based and embedded. The host processor 100provides at least one stimulus waveform to a stimulus memory 150 via astimulus memory interface 120. When the test requires a digitalstimulus, digital stimulus waveform 160 is retrieved from the stimulusmemory 150 and provided to the digital input of SUT 200. When the testrequires an analog stimulus, stimulus waveform samples retrieved fromstimulus memory 150 are provided to the DAC 180 via DAC input 170. TheDAC 180 converts the stimulus waveform samples into the analog stimuluswaveform 190 at a given sample rate. The analog stimulus waveform 190 isapplied to the analog input of SUT 200. A digital response waveform 210output from the SUT 200 is captured in a response memory 250. An analogresponse waveform 220 from the SUT 200 is first digitized by the ADC 230to produce a sampled response waveform 240 whose samples are stored inresponse memory 250. The samples in response memory 250 can be retrievedby host processor 100 via a response memory interface 270. The hostprocessor 100 then performs further analysis, measurements,calculations, statistics-gathering and display operations.

FIG. 2 illustrates an example of a configuration for an ATE system fromthe prior art. Host processor 100, in this case a mainframe computer, isattached to test head 300 via a mainframe to test head interface 315.Mainframe to test head interface 315 can be implemented by a variety oftechnologies using electrical or optical cables, Ethernet(10/100/1000/10G-baseT variants) networks, USB cables, other parallel orserial cables, or busses such as PCI, PCI Express (PCIe), VME, VXI, PXI,etc. Test head 300 includes stimulus memory 150 and response memory 250.As described with respect to of FIG. 1, stimulus memory 150 providesdigital stimulus waveform samples that are applied in a controlledsequence to the digital input of DUT 200. Alternatively, stimuluswaveform samples from stimulus memory can be converted to an analogstimulus waveform by a DAC (not shown in FIG. 2) that is applied to theanalog input of DUT 200. Similarly, response memory 250 stores thedigital response waveform or a digitized version of the analog responsewaveform from DUT 200. Examples of commercially available ATE testerswith this architecture include the Advantest T7611 and the CredenceSapphire D-40.

FIG. 3 is a block diagram of another configuration of a test system fromthe prior art. Host processor 100, in this case a personal computer,communicates with test chassis 330 using chassis interface 320. Testchassis 330 contains stimulus memory 150, whose output is used tostimulate the digital and/or analog inputs of SUT 200 via SUT interface340. Similarly, the digital and/or analog outputs of SUT 200 arecaptured in response memory 250 via SUT interface 340. Examples ofcommercially available PC-based test systems include products fromNational Instruments. The National Instruments PXI test system includesmultiple PXI (PCI eXtensions for Instrumentation) cards in a testchassis. The PC is implemented as a PXI card in the test chassis. Thetest chassis also contains a second PXI card that includes stimulusmemory and a third PXI card that includes response memory. All PXI cardsin test chassis can communicate using the chassis interface, also calleda bus, interconnect, or backplane. National Instruments also offers aproduct where the test chassis is an instrumentation peripheral thatuses the popular Universal Serial Bus (USB) to communicate with a laptopPC. In National Instruments compactDAQ™ product, the test chassiscontains up to eight removable cards. One of the compactDAQ cardsincludes stimulus memory and a second compactDAQ card includes responsememory. The test chassis communicates with the PC using a USB for thechassis interface. The compactDAQ card containing stimulus memory andthe compactDAQ card containing response memory communicate with the SUT.

The prior art systems of FIGS. 1, 2 and 3 have the following limitationsthat reduce testing efficiency:

-   -   Stimulus memory interfaces 120, 160 and 170 have limited        bandwidths,    -   Response memory interfaces 270, 210 and 240 have limited        bandwidths,    -   Mainframe to test head interface 315 and chassis interface 320        have limited bandwidths,    -   Stimulus memory 150 and response memory 250 have limited storage        capacities,    -   Delays are incurred when host processor 100 transfers stimulus        waveforms to stimulus memory 150 over interface 315 or 320 with        limited bandwidths,    -   Delays are incurred when host processor 100 retrieves the        response waveform samples via interface 315 or 320 from response        memory 250 prior to analysis.

The above limitations can be mitigated by compression and decompressionto the stimulus waveforms and response waveforms in accordance with thepresent invention.

Faster testing enabled by the present invention can provide substantialcost savings in the production of ICs. The average cost per hour oftesting by an ATE is $100 per hour. The cost savings can be economicallysignificant for the nearly $250 billion worth of ICs sold annually. Thecost of testing accounts for between 5% and 10%, conservatively, of thecost of silicon. An estimate of the cost of goods sold, includingtesting costs, is $100 billion, assuming a 60% gross margin. Based onthis estimate, between $5 billion and $10 billion is expended fortesting ICs annually. Reducing testing costs by 10% to 20% produces costsavings to the IC industry of $500 million to $2 billion.

The following example of IC testing illustrates how compression of thestimulus and response waveforms prior to transfer over a 1-gigabitEthernet connection reduces testing time. In this example, ahypothetical mixed-signal IC test system requires a digital stimuluswaveform and produces an analog response waveform. The stimulus waveformhas 1 million samples, a sample rate of 1 gigasamples/sec. (Gsamp/sec.)and 8 bits per sample. Assume that the IC under test is stimulated for 1msec., corresponding to the number of samples divided by the samplerate. The response waveform is captured for 1 msec. and digitized at asample rate of 1 Gsamps./sec. to produce 1 million response waveformsamples. Assume that applying compression described in the '147application (also described below with respect to a preferredembodiment) to the stimulus and response waveform samples results in 2:1lossless compression. The test system is an example of the architectureof FIG. 2, including a test head and a mainframe connected by a1-gigabit Ethernet link. Data are exchanged between the test head andmain frame at a rate of 125 megabytes/sec, or 125 megasamples/sec, viathe Ethernet link. Four steps required to test the DUT are as follows:

1) Load the AWG in the test head with 1 million samples,

2) Generate the stimulus and capture the response in the test head for 1msec.,

3) Transfer the response samples from the test head to the mainframe,and

4) Perform measurements in the mainframe.

The following table summarizes the testing times both with and withoutcompression for the above steps:

Test Time with- Test Time Test Step out Compression with Compresson LoadAWG memory in test head  8 msec.  4 msec. Run test and capture responsein digitizer memory in test head  1 msec.  1 msec. Transfer responsefrom test head to mainframe  8 msec.  4 msec. Make measurements inmainframe  8 msec.  8 msec. TOTAL 25 msec. 17 msec.

The above table shows that total test time is reduced from 25 msec. to17 msec., for a 30% reduction. For the average cost of testing by an ATEsystem of $100 per hour, 30% reduction in test time results in a savingsof $30 per hour for this particular example.

Other related art for test systems describes compression anddecompression of digital scan chains or scan vectors with an emphasis ondetecting defects in components of a device. Scan chains and scanvectors can be generated using automatic test pattern generation (ATPG),which takes as input an IC netlist and generates a fault list. Therelated art does not address the use of compression and decompression inconjunction with stimulus waveforms and captured response waveforms,each having analog or digital forms. Examples that address compressionof scan chains and scan vectors are described below. A significantdistinction between the present invention's compression and scan chaincompression is that scan chains are developed and used as sequences ofindividual ‘0’ or ‘1’ binary bits, while the present invention processessequences of groups of N binary bits (not individual ones and zeros),where each N-bit value represents one sample in a sampled data waveform.

In U.S. Pat. No. 7,093,174 (the '174 patent) the compaction of scanchain patterns that are used to verify the functionality of individualflip-flops in a digital DUT is described. Scan chains are used to teststrings of flip-flops (storage elements) in digital devices for properoperation. Using multiple scan chains, flip-flops and combinatoriallogic in each subset of a semiconductor device can be tested. Theorganization of scan chains in digital devices is usually automaticallydetermined by computer-aided design (CAD) tools. The goal of automatedscan chain insertion by CAD tools is to efficiently determine whetherflip-flops are operational. There is normally no relation between thefunctional operation of a DUT and the organization and access patternsof automatically or manually-generated scan chains. The '174 patent doesnot disclose the compression of digital waveforms that are laterdecompressed and applied to a DUT, in digital form or in analog form.The '174 patent does not disclose compressing the functional outputs ofa DUT, including digital response waveforms or digitized versions ofanalog response waveforms, prior to storage in a response memory.

U.S. Pat. No. 6,782,501 (the '501 patent) describes compression ofdigital scan vectors that include long strings of two-valued logiclevels, i.e. zeros and ones. The '501 patent cites the presence of“care” and “don't care” bits in the digital scan vectors (stimulus) tobe compressed. The scan vectors do not represent digital waveforms thathave multiple amplitude values. The '501 patent describes the generationof highly compact “signatures” (16-bit or 32-bit values) from the onesand zeros in the response signal. The “signature” of a response signalis generated through a series of logical and/or arithmetic operationsthat determine whether the signature of one scan chain is identical tothe signature of another scan chain. The “signatures” do not preserve orencode the individual response bits. These “signatures” are used forerror detection, just as are cyclic redundancy checks (CRC),error-detecting codes (EDC) and parity codes. The “signatures” do notrepresent the samples of a digital waveform or analog waveform andcannot be used to reconstruct the entire stream of bits from which thesignature was generated. The '501 patent does not disclose reversiblecompression of stimulus and response waveforms.

In addition to the limitations described above, the related art hasadditional disadvantages:

-   -   the time taken to write uncompressed stimulus waveform samples        into a stimulus memory is directly related to the number of        uncompressed samples in the stimulus waveform,    -   the time taken to read uncompressed waveform samples from a        response memory is directly related to the number of        uncompressed samples in the response waveform,    -   response capture devices usually do not make measurements, but        instead are only capable of capturing waveforms, whose        characteristics are later measured by a remote measurement        system, such as a computer or ATE mainframe.

SUMMARY OF THE INVENTION

An object of the present invention is to increase efficiency of test andmeasurement systems by compressing stimulus waveform and responsewaveforms before they are transferred over interfaces.

Another object of the present invention is to compress a stimuluswaveform before it is transferred over a data transfer interface or to astorage device. To generate a stimulus waveform, the compressed stimuluswaveform data are retrieved, decompressed and provided to the SUT as adigital stimulus or as an analog stimulus after analog-to-digitalconversion.

Another object of the invention is to compress a response waveform froma SUT so that compressed response waveform data are transferred over adata transfer interface and/or to a storage device. The compressedresponse waveform data are then decompressed for further analysis ordisplay.

Another object of the invention is to measure features, or parameters,of the response waveform by analyzing the uncompressed responsewaveform, the compressed response waveform data or the decompressedresponse waveform. The feature data can be provided in addition to orinstead of the compressed response waveform data.

Another object of the present invention is to provide alternativeconfigurations for test systems that include a stimulus decompressor. Inone configuration, a test system includes a stimulus source device thatincludes the stimulus decompressor and provides the decompressedstimulus waveform to the DUT. In another configuration, the stimulusdecompressor the DUT are integrated in a self-testing system.

Another object of the present invention is to provide alternativeconfigurations for test systems including the response compressor. Inone configuration, the test system includes a response processor devicethat includes the response compressor. The response processor receivesand compresses the response waveform from the DUT before transferring itto a data storage device or a data transfer interface. In anotherconfiguration, the response compressor the DUT are integrated in aself-testing system.

In another object of the invention, a remote host processor, such as aPC or mainframe, compresses one or more stimulus waveforms and storesthe compressed stimulus waveform data in the stimulus memory. The remotehost processor also retrieves the compressed response waveform data fromthe response memory and then decompresses the compressed responsewaveform data. The remote host processor may optionally makemeasurements or gather statistics that characterize the responsewaveform.

An advantage of the present invention is reduced testing time for theDUT because the time required for transfer of stimulus waveforms andresponse waveforms is decreased. The compressed waveform data will havethe effect of transferring more waveforms to and from the DUT over theinterfaces with limited bandwidths during a given time period.

Another advantage of the present invention is, in effect, storing anincreased number of stimulus waveforms and response waveforms instimulus and response memories, respectively, because the waveforms arecompressed. Alternatively, the amount of memory required may be reducedalong with a correspondingly reduced memory cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a stimulus and response test system,illustrated as testing a system under test (SUT) or a device under test(DUT), in accordance with the prior art.

FIG. 2 is a block diagram of a configuration example of automatic testequipment (ATE), in accordance with the prior art.

FIG. 3 is a block diagram of another configuration example of automatictest equipment (ATE), in accordance with the prior art.

FIG. 4 is a block diagram of use of compression and decompression forboth stimulus and response waveforms in a test system, in accordancewith a preferred embodiment.

FIG. 5 is a block diagram of an enhanced test system using compressionand decompression for stimulus waveforms, in accordance with a preferredembodiment.

FIG. 6 is a block diagram of an enhanced test system using compressionand decompression for response waveforms, in accordance with a preferredembodiment.

FIG. 7 a is a block diagram of a stimulus source with a decompressor foran analog stimulus, in accordance with a preferred embodiment.

FIG. 7 b is a block diagram of a stimulus source with a decompressor fora digital stimulus, in accordance with a preferred embodiment.

FIG. 7 c is a block diagram of a self-testing system with an integrateddecompressor and DAC, in accordance with a preferred embodiment.

FIG. 7 d is a block diagram of a self-testing system with an integrateddecompressor, in accordance with a preferred embodiment.

FIG. 8 a is a block diagram of a response processor with a compressorfor a sampled response waveform, in accordance with a preferredembodiment.

FIG. 8 b is a block diagram of a response processor with a compressorfor a digital response waveform, in accordance with a preferredembodiment.

FIG. 8 c is a block diagram of a self-testing system with an ADC andcompressor for processing an analog response waveform, in accordancewith a preferred embodiment.

FIG. 8 d is a block diagram of a self-testing system with a compressorfor processing a digital response waveform, in accordance with apreferred embodiment.

FIG. 9 a is a block diagram of a response processor includingcompression and waveform feature measurement, in accordance with apreferred embodiment.

FIG. 9 b is a block diagram of a self-testing system includingcompression and waveform feature measurement, in accordance with apreferred embodiment.

FIG. 10 a is a block diagram of a response processor that includeswaveform feature measurement of response waveform, in accordance with apreferred embodiment.

FIG. 10 b is a block diagram of a self-testing system with an integratedwaveform feature measurement processor, in accordance with a preferredembodiment.

FIG. 11 is an example of a waveform with level portions, edge portionsand glitches.

FIG. 12 is a block diagram of a compressor, in accordance with apreferred embodiment.

FIG. 13 is a block diagram of a compressor for a waveform having levelstates, edge states and glitch states in accordance with a preferredembodiment.

FIG. 14 is a block diagram for a level encoder for a compressor, inaccordance with an alternative embodiment.

FIG. 15 is a block diagram for an edge encoder for a compressor, inaccordance with a preferred embodiment.

FIGS. 16 a and 16 b give an example of edge encoding, in accordance witha preferred embodiment.

FIG. 17 gives an example of edge error encoding by a compressor, inaccordance with a preferred embodiment.

FIG. 18 is a block diagram for feature measurement based on waveformstates, in accordance with a preferred embodiment.

DETAILED DESCRIPTION

The use of compression and decompression in a test system to reduce testtime, increase memory capacity and increase memory bandwidth isdescribed in the following.

FIG. 4 is a block diagram of a preferred embodiment of a test systemthat includes compression and decompression of stimulus and responsewaveforms. The host processor 100, in this embodiment, is a PC ormainframe and is the source of the stimulus waveform samples 411.Stimulus compressor 410 compresses stimulus waveform samples 411 toproduce compressed stimulus waveform data 420. An optional stimuluscontroller 412 may control stimulus compressor 410 via stimuluscompression control 414 to provide control of the compression mode,further described below. The compressed stimulus waveform data 420 canbe stored in stimulus memory 150. To generate a stimulus waveform forthe SUT 200, the compressed stimulus waveform data are retrieved frommemory 150 and decompressed by the stimulus decompressor 450. For adigital stimulus, the decompressed stimulus waveform 454 from thestimulus decompressor 450 is provided directly as the digital stimuluswaveform to the system under test 200. For an analog stimulus, thedecompressed stimulus waveform 452 is converted to analog by the DAC180. The DAC provides the analog stimulus waveform 190 to the systemunder test 200.

The SUT 200 produces one or more output response waveforms, each ofwhich can be analog or digital. An analog response waveform 220 isconverted by ADC 230 to form a sampled response waveform 240 that isprovided to response processor 480. A digital response waveform 210 isprovided directly to response processor 480. The response processor 480compresses and, optionally, measures features of the response waveforms.Feature measurements will be described below with respect to FIGS. 9 a,9 b, 10 a, 10 b and 17. The response compressor 460 compresses sampledresponse waveform 240 and/or digital response waveform 210 to producecompressed response waveform data 470. The optional response controller492 selects lossless and lossy compression modes and compressionparameters. The response controller 492 provides response compressioncontrol 465 and to response compressor 460. The response decompressor490 decompresses the compressed response waveform data 470 to form adecompressed response waveform 491 for further analysis by the hostprocessor 100. The optional response controller 492 can control theoperations of response decompressor 490 via response decompressioncontrol 416.

The stimulus controller 412 and response controller 492 can provideselection of compression mode and respond to input from a user. Thecompression modes for stimulus compressor 410 and response compressor460 include lossless modes and lossy modes. For example, under somecircumstances stimulus compressor 410 will generate lossless-compressedwaveforms, whose values after decompression by stimulus decompressor 450will be identical to the original stimulus waveform. In othercircumstances, stimulus compressor 410 will generate lossy-compressedwaveforms that require less storage and/or bandwidth than either thelossless-compressed waveform or the original, uncompressed waveform. Inthe case of lossy compression, several additional alternatives areavailable. Lossy compression may provide a compressed waveform whosebandwidth or bit rate is user-specified. In other instances lossycompression may provide a compressed waveform whose quality isuser-specified. For lossy compression modes, parameters representing thedesired the bit rate (including compression ratio) or signal quality(including signal-to-noise ratio [SNR], distortion level, etc.) may bepassed to stimulus compressor 410, via stimulus compression control 414and, optionally, to stimulus decompressor 450 via stimulus decompressioncontrol 455. Response controller 492 provides similar compressioncontrol for the response compressor 460. In addition, responsecontroller 492 can select any features measurements that will begenerated by further processing the response waveform data.

In this description, the host processor 100 functions as the source ofthe original stimulus waveform samples 411 to be compressed or thedestination for the response waveform data, compressed, decompressed oruncompressed, depending on the application. Host processor 100 can makemeasurements on the response waveform data appropriate for theapplication. Host processor 100 can be implemented by one or moreprocessors in a PC or mainframe, as indicated by FIGS. 1-6. Hostprocessor 100 can also be implemented in alternative locations.Referring to FIG. 2, host processor 100 can be implemented on a separatecontroller card in the test head 300 or a CPU integrated with stimulusmemory 150 and/or response memory 350. Referring to FIG. 3, hostprocessor 100 can be implemented in a separate controller card in testchassis 330 coupled to stimulus memory 150 and/or response memory 350.

FIG. 5 is a block diagram of an embodiment wherein only the stimuluswaveform is compressed and decompressed. Stimulus compressor 410,stimulus decompressor 450 and optional stimulus controller 412 are thesame as described with respect to FIG. 4. Unlike the embodiment of FIG.4 the response waveform is not compressed or decompressed, but is storedin response memory 250 as described previously for the prior art testsystem of FIG. 1.

FIG. 6 is a block diagram of an embodiment wherein only the responsewaveform is compressed and decompressed. The response processor 480,response compressor 460, response decompressor 490 and optional responsecontroller 492 are the same as described with respect to FIG. 4. Theinput stimulus waveform is stored in uncompressed form in the stimulusmemory 150, as described for the prior art test system of FIG. 1.

FIGS. 7 a-d shows various possible configurations for compressing anddecompressing the stimulus waveform. FIG. 7 a is a block diagram of anembodiment providing an analog stimulus where the compressed stimuluswaveform data 420 is transferred from the stimulus compressor 410 to astimulus source 710. The stimulus source 710 includes a stimulus memoryor network 750 that transfers and/or stores the compressed stimuluswaveform data 420. The stimulus decompressor 450 retrieves thecompressed stimulus waveform data 420 from the memory or network 750 andproduces decompressed stimulus waveform 452. The DAC 180 converts thedecompressed stimulus waveform 452 to produce an analog stimuluswaveform 190 for the SUT 200.

FIG. 7 b is a block diagram of an embodiment providing a digitalstimulus where the compressed stimulus waveform data 420 is transferredto the stimulus source 710 as described for FIG. 7 a. The stimulusdecompressor 450 provides the decompressed stimulus waveform 454 as thedigital stimulus waveform for the system under test 200.

FIGS. 7 c and 7 d show embodiments where the stimulus decompressor 450and the SUT 200 are integrated in a self-testing system 720. Theseembodiments are applicable to BIST architectures. FIG. 7 c is a blockdiagram of an embodiment providing an analog stimulus where the stimulusdecompressor 450 is integrated with the SUT 200 in a self-testing system720. The compressed stimulus waveform data 420 is transferred from thestimulus memory or network 750 to the stimulus decompressor 450 withinthe self-testing system 720. The DAC 180 converts the decompressedstimulus waveform 452 to form the analog stimulus waveform 190 input tothe analog subsystem 730 of the SUT 200.

FIG. 7 d is a block diagram of an embodiment providing a digitalstimulus where the stimulus decompressor 450 is integrated with the SUTthe self-testing system 720. The decompressed stimulus waveform 454 isprovided as the digital stimulus waveform directly to the digitalsubsystem 740 of the SUT 200. The stimulus decompression control 455 isoptional in the embodiments of FIGS. 7 a-d, as described with respect toFIG. 4. Also in FIGS. 7 a-d, stimulus decompressor 450 may optionallyinclude local memory (not shown in FIGS. 7 a-d) to store one or morecompressed stimulus waveforms.

FIGS. 8 a-d depict various configurations for compressing the responsewaveform. FIG. 8 a is a block diagram of an embodiment where theresponse processor 810 includes response compressor 460 and a memory ornetwork 850. The memory or network 850 stores and/or transfers thecompressed response waveform data 470 to the host processor 100. In FIG.8 a, the SUT 200 produces an analog response waveform 220 that isconverted to digital form by ADC 230 prior compression by responsecompressor 460. In FIG. 8 b, the SUT 200 produces the digital responsewaveform 210 that is then compressed by response compressor 460. Theself-testing systems of FIGS. 8 c and 8 d can be implemented in BISTarchitectures. In FIG. 8 c, the self-testing system 820 includes an ADC230 and response compressor 460. The SUT's analog subsystem 830 providesan analog response waveform 220 to ADC 230 for conversion to sampledresponse waveform 240. The response compressor 460 provides thecompressed response waveform data as the self-testing system output 800to the memory or network 850. In FIG. 8 d, the self-testing system 820includes the response compressor 460. The SUT's digital subsystem 840produces the digital response waveform 210 for compression by responsecompressor 460 to produce the self-testing system output 800. In FIGS. 8a-d the response compression control 465 is optional, as described withrespect to FIG. 4. In FIGS. 8 a-d, response compressor 460 mayoptionally include local memory (not shown in FIGS. 8 a-d) to store oneor more compressed response waveforms.

Alternative embodiments for self-testing systems may include both thestimulus decompressor 450 and the response compressor 460. For example,an embodiment of a self-testing system providing an analog stimuluswaveform 190 and an analog response waveform 220 includes the elementsof self-testing system 720 of FIG. 7 c and self-testing system 820 ofFIG. 8 c. An embodiment of a self-testing system providing adecompressed stimulus waveform 454 and a digital response waveform 210includes the elements of self-testing system 720 in FIG. 7 d andself-testing system 820 in FIG. 8 d. An embodiment of a self-testingsystem providing an analog stimulus waveform 190 and a digital responsewaveform 210, includes the elements of self-testing system 720 in FIG. 7c and self-testing system 820 in FIG. 8 d. An embodiment of aself-testing system providing a decompressed stimulus waveform 454 andan analog response waveform 220 includes the elements of self-testingsystem 720 in FIG. 7 d and self-testing system 820 of FIG. 8 c.

Response processor 480 can, optionally, measure parameters, or features,of the response waveform that are useful for subsequent analysis.Feature measurements can be performed on compressed response waveformdata, decompressed response waveform or a digital form of responsewaveform before compression. FIGS. 9 a and 9 b are block diagrams thatinclude compressing the response waveform and measuring the features. InFIG. 9 a, the response processor 810 includes the response compressor460 and the waveform feature processor 900. The response compressor 460compresses the digital response waveform 210 or the sampled responsewaveform 240 from an analog response to form compressed waveform data910. The waveform feature processor 900 measures features of thecompressed waveform data 910. Alternatively, the waveform featureprocessor 900 can measure features of the uncompressed response waveform210 or 240 or a combination of uncompressed and compressed data.Compressed data and features are provided as input 990 to the memory ornetwork 250. In FIG. 9 b, the self-testing system 820 includes responsecompressor 460 and waveform feature processor 900. The responsecompressor 460 and the waveform feature processor 900 perform the samefunctions as described with respect to FIG. 9 a. The optional responsecompression control 465, in addition to the previously describedcompression control, can also control the waveform feature processor byselecting the features to be measured as well as additional calculationparameters. Alternative embodiments for self-testing systems thatprovide both stimulus and response can include the elements ofself-testing system 820 in FIG. 9 b for response and the elements ofself-testing system 720 of FIG. 7 c for analog stimulus or FIG. 7 d fordigital stimulus, as described previously with respect to FIGS. 8 c and8 d.

In some applications, the waveform features contain the usefulinformation so the compressed response waveform data are not required.FIGS. 10 a and 10 b show embodiments where only the features of theresponse waveforms are measured. In FIG. 10 a, response processor 810includes the waveform feature processor 900 that extracts features fromthe response waveform 210 or 240. The extracted feature date are input992 to the memory or network 250. In FIG. 10 b, the self-testing system820 includes the waveform feature processor 900. The waveform featureprocessor 900 calculates the features of the response waveform 210 or240 generated by the digital or analog subsystems, respectively, to formextracted feature data as input 992 to the memory or network 250. ForFIGS. 10 a and 10 b, the optional response compression control 465 canselect the features to be measured as well as additional calculationparameters. Alternative embodiments for self-testing systems thatprovide both stimulus and response can include the elements ofself-testing system 820 in FIG. 10 b for the response and the elementsof self-testing system 720 of FIG. 7 c for analog stimulus or FIG. 7 dfor digital stimulus, as described previously with respect to FIGS. 8 cand 8 d.

Alternative embodiments of the present invention include configurationsthat provide more than one stimulus waveforms on multiple inputs of aSUT in any combination of analog and/or digital stimuli. Stimuluscompressor 410 can be implemented by multiple compressors in parallel.Stimulus decompressor 450 can include multiple decompressors inparallel, each providing the stimulus waveform for a different input ofthe SUT. Alternatively, stimulus compressor 410 and/or stimulusdecompressor 450 can compress/decompress the stimulus waveform for eachSUT input serially. Alternative embodiments also include configurationsthat receive and process multiple response waveforms from multipleoutputs of a SUT in any combination of analog and/or digital responsewaveforms. Response compressor 460 can include multiple parallelcompressors, each compressing the response waveform from one of the SUToutputs. Waveform feature processor 900 can also include multipleparallel waveform feature processors. The response decompressor 490 canalso include multiple parallel decompressors. Alternatively, one or moreof the response compressor 460, waveform feature processor and responsedecompressor 490 can operate serially on the multiple responsewaveforms. In another alternative, multiple decompressed stimuluswaveforms can be provided to two or more DUTs or SUTs, thus implementinga stimulus generator for multi-site ATE, where two or more devices canbe tested in parallel.

The stimulus compressor 410 and response compressor 460 apply losslessor lossy compression methods to their respective input waveform samples.The present inventor describes compression algorithms for bandlimitedwaveforms in detail in the '852 patent. The description includes bothlossless and lossy compression, selection of compression controlparameters according to a desired compression ratio or desireddecompressed signal quality, and measurement of signal parameters,including center frequency and noise floor. In the '771 application thepresent inventor describes efficient compression algorithms for waveformsamples output from a TIADC. The algorithms described therein would beapplicable to embodiments of the present invention if the ADC 230comprises a TIADC. In the '147 application the present inventordescribes efficient algorithms for compressing waveforms with two ormore recurring waveform states. The algorithms described thereinseparate the waveform samples into different waveform states and encodethe samples according to each waveform state. Also described are methodsfor measuring useful features and their statistics using the waveformsamples and the compressed waveform data. The '852 patent, the '771application and the '147 application also include descriptions of thecorresponding decompression methods that are applicable to the stimulusdecompressor 450 and the response decompressor 490. The compression anddecompression algorithms described involve simple computations so thatcompression and decompression can be performed in real time, or at leastas fast as the sample rate of the waveform samples.

A preferred embodiment of the present invention applies when thestimulus and/or response waveform has two or more recurring waveformstates. This type of waveform is common in test and measurement systems.Compression methods described in the '147 application for waveformshaving level portions and edge portions can achieve compression ratiosof about 2:1 to 3:1 for lossless compression and greater compressionratios for lossy compression. The following description for FIGS. 11through 17 includes excerpts from the text and figures of the '147application. FIG. 11 (FIG. 4 in the '147 application) is an example of awaveform that has recurring characteristics, including level portionsand edge portions. In addition to the level portions and edge portions,the waveform has “glitches” that include waveform samples that arediscontinuous with the pattern of neighboring samples. Thecharacteristics of the waveform in FIG. 11 include a high level portion1401 having a high level amplitude, a low level portion 1402 having alow level amplitude, a rising edge 1403, a falling edge 1404, a positiveglitch 1406 that deviates in the positive direction, and a negativeglitch 1405 that deviates in the negative direction. Because theamplitudes of most of the samples cluster around specific level states,specifying an encoder for each level state will provide more efficientcompression than applying the same encoder to all samples. The waveformcharacteristics can also include multiple amplitude levels, frequencystates and phase states.

FIG. 12 (FIG. 7 in the '147 application) is a block diagram of apreferred embodiment for the stimulus compressor 410 and/or the responsecompressor 460 for compressing waveform samples with at least twowaveform states. Waveform state processor 1702 determines the waveformstates of the waveform samples 1100 and produces waveform state samplevectors for encoder input 1707. Referring to FIG. 4, the waveformsamples 1100 correspond to the stimulus waveform samples 411 input tostimulus compressor 410, the digital response waveform samples 210 inputto the response compressor 460 or the sampled response waveform samples240 input to the response compressor 460. Each waveform state samplevector includes consecutive waveform samples in a particular waveformstate. Encoder 1708 includes a waveform state encoder for each waveformstate. The waveform state sample vectors are directed to thecorresponding waveform state encoder. For this example, waveform statesample vectors corresponding to the first waveform state are input 1707a to the first waveform state encoder 1708 a and waveform state samplevectors corresponding to the second waveform state are input 1707 b towaveform state encoder 1708 b. The waveform state encoders 1708 a and1708 b apply encoding specific for the waveform state to the waveformstate sample vectors to produce compressed waveform data at the encoderoutput 1711. Depending on the application, the encoder output 1711 maybe either maintained as separate compressed data stream outputs 1711 aand 1711 b or multiplexed into a single stream. Maintaining separatecompressed data streams is advantageous when the compressed data for thedifferent waveform states are stored in separate memory segments definedfor each waveform state. It is also useful when further analysis of thecompressed data for feature measurements or for generating statistics isrequired. Alternatively, compressed data stream outputs 1711 a and 1711b can be multiplexed into a single stream for transfer over a high-speedinterface. User control 1700 allows a user to select the waveform statesto be captured and compressed.

For the waveforms illustrated in FIG. 11, the waveform states correspondto two level states, two edge states and two glitch states. The waveformstate processor 1702 selects waveform samples in a level portion for alevel state of the waveform. The encoder for a given level state, forinstance waveform state encoder 1708 a, encodes all samples in thatlevel state. Samples that are not in a level portion are defined to bein an edge portion of the sampled waveform. The waveform state processor1702 determines an edge state for samples in each edge portion. Thewaveform state processor 1702 also detects glitch portions of thesampled waveform.

FIG. 13 (FIG. 8 in the '147 application) is a block diagram of apreferred embodiment of the stimulus compressor 410 and/or the responsecompressor 460 for waveform samples having level states, edge states andglitch states. The waveform state processor 1702 includes statedetermination logic 1704 and state capture mask register 1706. Waveformsamples 1100 are input to state determination logic 1704 of the waveformstate processor 1702. State determination logic 1704 applies algorithmsdescribed below for determining samples that are in level states, edgestates and glitch states. The samples detected for the different statescomprise waveform state sample vectors 1707. The waveform state samplevectors 1707 are transferred to their respective encoders. Level statesample vectors form input 1707 a to level encoder 1710. Level encoder1710 includes encoders for each level state. For example, for two levelstates, there are two level encoders 1710. Edge state sample vectorsform input 1707 b to edge encoder 1712. Edge encoder 1712 includes anencoder for rising edge samples and an encoder for falling edge samples.Glitch state sample vectors form input 1707 c to glitch encoder 1714.The state determination logic 1704 also provides a state indicator 1705to the state capture mask register 1706. The state capture mask register1706 allows selective encoding of the various states according to usercontrol 1700. For example, state capture mask register 1706 may directthat only samples in a high level state are captured and encoded whenBit 0=1 and Bits 1 to 5 are zero. For another example, state capturemask register 1706 may direct that only samples in high, or positive,glitches and low, or negative, glitches are captured when Bit 4=1 andBit 5=1 and Bits 0 to 3 are zero. Waveform state encoders 1710, 1712 and1714 encode the waveform state sample vectors received via inputs 1707a, 1707 b and 1707 c, respectively, to form compressed waveform data atthe encoder output 1711.

In a preferred embodiment, the level encoder 1710 includes Huffmanencoding of the samples in the level state sample vector. In Huffmanencoding, the number of bits in the token representing an amplitudelevel is inversely proportional to the frequency of samples having thatamplitude level.

In an alternative embodiment, the level encoder 1710 encodes thedifference between each sample in the level state sample vector and alevel state parameter. The level state parameter can be the meanamplitude for samples in that level state or the amplitude threshold forthat level state. The difference samples can then be Huffman-encoded orquantized. For quantizing, the number of bits per sample is fixed,unlike Huffman encoding. Quantizing can provide lossy encoding byreducing the number of bits allocated per sample. For example, if therange of values requires three bits per sample for an exactrepresentation, quantizing to two bits per sample provides additionalcompression, although error is introduced. The user can determine whenthe additional compression justifies the introduction of error.

Another useful level parameter is the level's run length. The level'srun length can be measured in number of samples. Alternatively, when therun lengths are multiples of a minimum run length, they can berepresented by the values of the multiples. For bauded signals, theminimum run length corresponds to the time interval for one baud. For arectangular pulse sequence, the minimum run length corresponds to thetime interval for one pulse. For convenience, the number of samples inthe minimum run length for a level will be referred to as the number ofsamples per baud and a measure of run length will be referred to as thenumber of bauds. However, this is not intended to narrow the scope ofthe invention to bauded signals only. Using the number of bauds tomeasure run length may result in leftover samples because the ratio ofthe baud rate to the sample rate may not be a whole number. Both the runlength in bauds and number of leftover samples can be Huffman-encoded.

FIG. 14 (FIG. 13 in the '147 application) is a block diagram of analternative embodiment for the level encoder 1710 that encodes levelparameter vectors. The measure parameters block 1750 measures one ormore parameters of the level state sample vector input 1707 a to form alevel parameter vector 1751. For example, the amplitude threshold, meanvalue and run length of the level can be measured to form a levelparameter vector 1751. Vector encoding can be applied to the levelparameter vector 1751 using a predetermined set 1754 of level patternvectors and associated level vector codes. The set 1754 of level patternvectors may be determined during a training period, as described in the'147 application. The selecting block 1752 compares one or moreparameters of the level parameter vector 1751 to the correspondingparameters of the level pattern vectors of the set 1754 to select alevel pattern vector 1753 to represent the parameter vector 1751. Theselect code block 1758 assigns the level code 1759 corresponding to theselected pattern vector 1753. If desired, calculate error block 1756 cancalculate a parameter error 1757 between the level parameter vector 1751and corresponding parameters 1755 of the selected pattern vector 1753.Calculating the parameter error 1757 is useful for observing variationsin the parameters over time. The encode error block 1760 then encodesthe parameter error 1757 or quantizes the error 1757 prior to encodingit. The level vector code 1759 and the encoded error 1761 are input tothe form level encoder output block 1762 where they are used to formpart of the level encoder output 1711 a. Differences between the levelparameter vectors 1751 and the selected pattern vectors 1753 may changein later regions of the waveform. For instance, baud rate variation,amplitude drift and nonlinearities can be tracked using the encodedparameter error 1761.

Reconstructing the waveform samples using the selected level patternvector 1753 will not always regenerate the same waveform samples in thelevel state sample vector 1707 a, resulting in lossy encoding. Losslessencoding of the samples of the level state sample vector 1707 a can alsobe achieved. The build template block 1764 uses the selected patternvector to build a corresponding level state template 1765. The buildtemplate block 1764 can be a look-up table of level state templatescorresponding to level pattern vectors in the set 1754. Subtractor 1766subtracts the level state template 1765 from the level state samplevector 1707 a to form sample error 1767. The encode sample error block1768 then encodes the sample error 1767. When the encode sample errorblock 1768 applies lossless encoding, the level state sample vectorencoding will be lossless. Conversely, when the encode sample errorblock 1768 applies lossy encoding, the level state sample vectorencoding will be lossy. The encoded sample error 1763 is input to theform level encoder output block 1762 where it forms part of the levelencoder output 1711 a.

For decompression by stimulus decompressor 450 and/or responsedecompressor 490, the level state sample vector is reconstructed fromthe selected code 1759 and the encoded sample error 1763. A decoder usesthe code 1759 to select a corresponding level state template, whichwould be the same as the corresponding level state template 1765. Theencoded sample error 1763 is decoded to form a reconstructed sampleerror. The decoder adds the reconstructed sample error to thecorresponding level state template to form a reconstructed level statesample vector. For lossless encoding, the samples in the reconstructedlevel state sample vector would have the same amplitudes as the samplesin the level state sample vector 1707 a.

For embodiments that include response waveform feature measurements bythe waveform feature processor 900, the level encoder 1710 includesfeature extraction. The measure parameters block 1750 can also measurefeatures of the level state sample vector in addition to the parametersused for the encoding embodiment depicted in FIG. 14, thus performingfunctions of the waveform feature processor 900 in FIGS. 9 a and 9 b.Alternatively, measurement of one or more features of each level statesample vector can represent all the samples in the level state samplevector. This approach includes functions of the waveform featureprocessor 900 in FIGS. 10 a and 10 b. Since a waveform feature normallyrequires less storage than the samples from which a feature wasextracted, storage of waveform features is also a form of compression.The user can select which features are stored for a given waveformstate. The user can balance the tradeoffs between the level of detailand the amount of storage required. High levels of compression areachieved when a single feature is stored for each waveform state samplevector. Lower levels of compression are achieved when more waveformfeatures or information about each individual sample in the waveformstate vector is captured and stored. Examples of single-featurerepresentation include the mean, median or mode of the samples in eachlevel state sample vector. Examples of a two-feature representation foreach level state sample vector can include the mean and variance of itssamples, the mean and standard deviation of its samples, or the minimumand maximum samples. The measured features can be arranged to form alevel state feature vector that corresponds to the level state samplevector.

Prior to level encoding, the waveform state processor 1702 detects thesamples belonging to each level state in order to form level statesample vectors, as described with respect to FIG. 13. The statedetermination logic 1704 in FIG. 13 detects levels using predeterminedamplitude thresholds and predetermined duration thresholds. For awaveform with two level states, such as the example waveform shown inFIG. 11, the state determination logic 1704 applies at least twoamplitude thresholds, a lower bound for the high amplitude level stateand a higher bound for the low amplitude level state. When only a lowerbound threshold is applied, the samples of the high amplitude levelstate will have an amplitude range from the lower bound threshold to themaximum sample amplitude and the samples of the low level state willhave an amplitude range from the upper bound threshold to the minimumsample amplitude. These ranges can be further restricted by applying, inaddition, an upper bound threshold to the high amplitude state and alower bound threshold to the low amplitude state. In addition to theamplitude thresholds, the state determination logic 1704 appliesduration thresholds. The amplitude threshold criteria for each waveformstate must be met by consecutive samples whose duration is approximatelyone baud interval or greater, when glitches are absent. As describedpreviously for measuring run length, when the number of samples per baudis fractional, there can be “leftover” samples. Many algorithms forapplying thresholds to waveform samples for detection are known to thoseskilled in the art.

Waveform samples positioned between adjacent level portions withdifferent level amplitudes, or different level states, are defined asedge portions. Referring to FIG. 13, state determination logic 1704selects samples for edge state sample vectors 1707 b input to edgeencoder 1712. FIG. 15 (also FIG. 15 in the '147 application) is a blockdiagram of a preferred embodiment for edge encoder 1712. The edgepattern vector selector 1800 selects a corresponding edge pattern vector1801 and a corresponding edge pattern index 1803 from a predeterminedset of edge pattern vectors in an edge pattern dictionary 1802 torepresent an input edge state sample vector 1707 b. The edge patternvectors included in the edge pattern dictionary 1802 can be determinedduring training as described in the '147 application with respect toFIGS. 16 and 17 therein. Subtractor 1804 subtracts the correspondingedge pattern vector 1801 from the edge state sample vector 1707 b toform the edge error 1805. The encode error block 1806 encodes the edgeerror 1805 to form encoded edge error 1807. A preferred embodiment forencode error block is described below with respect to FIG. 16. The edgepattern code selector 1808 selects the code assigned to thecorresponding edge pattern index 1803 in accordance with the edgepattern codebook 1834. The selected edge code 1809 and the encoded edgeerror 1807 are input to the form edge encoder output block 1810 forforming part of the edge encoder output 1711 b. In alternativeembodiments, edge encoder 1712 can provide lossless or lossy encoding tothe edge state sample vector 1707 b. When the encode error block 1806applies lossless encoding to the edge error 1805, the overall edgeencoding process is lossless. The encode error block 1806 can performlossy encoding by quantizing the edge error 1805 to fewer bits. The edgeencoder 1712 can also perform lossy encoding using the edge pattern code1809 alone to represent the edge state sample vector 1707 b. In thisembodiment, the error 1805 is not calculated so the subtractor 1804 anderror encoder 1806 are not used.

The stimulus decompressor 450 or response decompressor 490 that receivesthe edge pattern code 1809 and the encoded edge error 1807 canreconstruct the amplitudes of the samples of the original edge statesample vector 1707 b. The stimulus decompressor 450 or responsedecompressor 490 decodes the edge pattern code 1809 to determine thecorresponding edge pattern vector. The samples of the edge state samplevector are reconstructed by adding the decoded edge error to thecorresponding edge pattern vector. For lossless encoding, the amplitudesof the samples in the reconstructed edge state sample vector will equalthose of the original edge state sample vector 1707 b. For lossyencoding, the amplitudes of the samples in the reconstructed edge statesample vector will approximate those of the original edge state samplevector 1707 b.

FIGS. 16 a and 16 b (FIGS. 18a and 18b in the '147 application) give anexample of encoding a rising edge sample vector. FIG. 16 a gives therising edge dictionary 1848, the edge pattern indices 1850 and the edgepattern codes 1852 for the example. The edge pattern codes are Huffmancodes based on the frequencies of occurrence of the pattern vectors.FIG. 16 b gives an example of encoding a new rising edge sample vector1854. Referring to FIG. 15, the rising edge sample vector 1854 is theedge encoder input 1707 b and the rising edge dictionary 1848 isincluded in the edge pattern dictionary 1802. Edge pattern selector 1800selects edge pattern vector 1856 for its output 1801. The subtractor1804 calculates the edge error vector 1858 as the edge error 1805. Thevalue of the corresponding edge pattern index 1857 is 4, which is input1803 to the select edge pattern code block 1808. The edge pattern codes1852 form part of the edge pattern codebook 1834. The select edgepattern code block selects the edge pattern code 1859 which is the token“11” for its output 1809.

FIG. 17 (FIG. 19 in the '147 application) gives an example of encodingthe edge error in accordance with a preferred embodiment. Table Aincludes tokens used to encode the error samples based on the range oferror in an edge error vector. When large errors are less likely tooccur than smaller errors, codes are assigned based on the error range.The exponent column A1 assigns tokens that represent the ranges of errorindicated in column A2. The error column A3 gives the error valueswithin the corresponding range. The tokens column A4 gives the tokensassociated with the error values for the corresponding range. Theencoded edge 1860 includes the binary coded edge pattern index 1860 a,“100”. In this example, edge pattern code is simply the binary value ofthe edge pattern index, 4. The encoded edge 1860 also includes anencoded error portion 1860 b and 1860 c. The portion 1860 b is the tokenindicating the range of error of (0, −1). The portion 1860 c includesthe encoded edge error samples (0, 0, 1, 0, 1). These correspond to edgeerror samples (0, 0, −1, 0, −1).

As the above examples show, when the waveform has little or no noise,the selector 1800 can select a corresponding edge pattern vector 1801 bycomparing corresponding samples of the edge state sample vector and edgepattern vector. Comparing as few as one or two samples can besufficient, especially since any edge error is encoded. For more noisywaveforms, the edge codebook entry that is selected has the smallestabsolute error, the smallest average error, or the smallest of anotheruser-specified error metric or combination of two or more metrics. Manyminimum-distance error metrics are known to those skilled in the art.

As described previously with respect to level encoder 1710, featureextraction can be performed along with compression. The waveform featureprocessor 900 can calculate edge features. The user can select featuresuseful for the analysis at hand. For edge states, useful featuresinclude rise and fall times and zero crossing times. Zero crossing timescan further be used to extract jitter information, which is growing inimportance as industry-standard serial busses such as PCI Express,Serial ATA, and Serial RapidIO become more popular. In addition,features of multiple edges used to determine positive and negative pulsewidths and duty cycle can be calculated. These features can be derivedfrom edge pattern vectors, edge state sample vectors or both. The timescorresponding to zero crossing, 10% and 90% amplitudes for rise/falltimes and threshold amplitudes for pulse width and duty cyclemeasurements can be calculated using well-known methods ofinterpolation. The calculated times are relative to the initial sampletime of the edge pattern vector or edge state sample vector. Because theedge pattern vectors are representative of edge state sample vectors, itis efficient to analyze edge pattern vectors individually or in groupsfor feature extraction. For example, groups of pattern vectors can beaveraged and interpolated to find an average zero crossing time.

In an alternative embodiment, a polynomial representation is used forextracting edge features. For example, the 10% to 90% rise time can becalculated once based on the polynomial model and apply to all edgesrepresented by that polynomial. For example, the zero crossing intervalis determined once relative to the initial point of the polynomial modelfor a rising edge. The zero crossing relative to the initial sample of aparticular rising edge is determined by subtracting the temporal offsetof the rising edge sample vector and from the zero crossing interval.

The feature measurements can be encoded and appended to the encoded edgestate sample vectors, in accordance with the embodiments of FIGS. 9 aand 9 b. Alternatively, one or more feature measurements can representall the samples in the edge state sample vector, as described previouslywith respect to level states, in accordance with the embodiments ofFIGS. 10 a and 10 b. The features are arranged to form an edge statefeature vector that corresponds to the edge state sample vector. A timestamp can be included with the feature data in the edge state featurevector to preserve its temporal information.

Referring to FIG. 13, the state determination logic 1704 includes aglitch detector. A glitch detector applies amplitude and durationthresholds to the waveform samples 1100. The user can specify an uppertolerance threshold for detecting positive glitches and a lowertolerance threshold for negative glitches. The duration threshold valueis less than a baud interval. A positive glitch is detected when theamplitudes of consecutive samples rise above then fall below the uppertolerance during a time interval that is less than the durationthreshold. A negative glitch is detected when the amplitudes fall belowthen rise above the lower tolerance during a time interval that is lessthan the duration threshold.

The glitch detector provides glitch samples for a glitch state samplevector 1707 c input to glitch encoder 1714. Glitches can be representedin a variety of ways, including:

1) glitch duration (sample count) encoding,2) glitch mean value,3) glitch maximum and minimum values,4) glitch sample values,5) quantized glitch sample values,6) glitch magnitude,7) other glitch encoding techniques

The features extracted from the pattern and sample vectors of level andedge states are used to determine commonly used measurements. Aspreviously described, feature vectors can be formed and appended topattern vectors and compressed sample vectors. The feature vectors forcompressed sample vectors can include time stamps that are used whenmeasuring features across more than one edge or level. Statistics foredge and level features and other measurements using those features canbe computed and analyzed. Useful measurements related to time includethe following.

-   1) Rise time and fall time—10% to 90% rise or fall time and 20% to    80% rise or fall time intervals can be calculated for individual    edge pattern vectors or edge state sample vectors.-   2) Zero crossing time can be calculated for individual edge pattern    vectors or edge state sample vectors relative to the initial sample    of the vector.-   3) Positive or negative pulse width with respect to a threshold,    such as 50% of level amplitude, requires features from two    consecutive edges. The time interval corresponding to the threshold    crossing (TX) on each edge is calculated relative to the initial    sample of the respective edges. The pulse width (PW) calculation    also requires the time interval between the two edges which can be    calculated using time stamps (TS) for the initial samples of the    respective edges as follows:

PW=TS₂−TS₁−TX₁+TX₂

-   -   Alternatively, the run length (RL) of the level state between        the edges and the run length (RE₁) of the first edge can be used        to calculate pulse width (PW) as follows:

PW=RE₁−TX₁+RL+TX₂

-   4) Period measured as the time interval between zero crossings, or    other amplitude threshold crossings, of consecutive rising edges is    calculated across three consecutive edges and the intervening level    portions. The zero (or other threshold) crossing time intervals (TZ)    and time stamps (TS) relative to the initial samples of the two    rising edges are used to calculate the period (P) as follows:

P=TS₂−TS₁−TZ₁+TZ₂

-   -   Alternatively, the period P can be calculated using run lengths        of the intervening positive and negative level portions (RL₁ and        RL₂) and the first and middle edge portions (RE₁ and RE_(M))        between the level portions as follows:

P=RE₁−TZ₁+RL₁+RE_(M)+RL₂+TZ₂

Useful measurements related to amplitudes include the following.

-   1) Top and maximum amplitudes can be measured for high level state    sample vectors or level pattern vectors. For levels with overshoot,    the maximum amplitude (max) is measured in the adjacent overshoot    portion.-   2) Base and minimum amplitudes can be measured for low level state    sample vectors or level pattern vectors. For levels with undershoot,    the minimum amplitude (min) is measured in the adjacent undershoot    portion.-   3) Amplitude (Amp) value between low and high levels is found by:

Amp=top−base

-   4) The peak to peak (PP) value between low and high levels is found    by:

PP=max−min

Useful measurements of glitch parameters include the following:

-   -   1) Positive glitch duration and amplitude.    -   2) Negative glitch duration and amplitude.    -   3) Percentage of bauds or pulses with glitches.

Jitter can also be measured using the level and edge features. The zerocrossing times calculated for the edge state sample vectors can be usedto measure timing jitter, with reference to a recovered clock signal(also called the “golden clock”), or with reference to the previousrising or falling edge. The level features calculated for the levelstate sample vectors can be used to measure amplitude jitter, which canoften be correlated with the noise floor or signal-to-noise ratio (SNR)of the signal.

FIG. 18 is a block diagram of an embodiment of waveform featureprocessor 900 for a waveform having waveform states. This embodiment isuseful for the configurations illustrated in FIGS. 10 a and 10 b. Thedigital response waveform 210 or sampled response waveform 240corresponds to the waveform samples 1100. The state determination logic1704 detects the states of the waveform samples 1100 and forms thewaveform state sample vectors 1707 a and 1707 b. State featuremeasurement blocks 1010 a and 1010 b measure features of the respectivewaveform state sample vectors. For example, for waveforms having levelstates and edge states, the state feature measurement blocks 1010 a and1010 b and calculate the level state features and the edge statefeatures as described above. Feature statistics processors 1020 a and1020 b calculate statistics on the measured features for each state,such as averages, variances, maximums, minimums, modes, etc. Thecombiner 1030 organizes the feature measurements and statistics for thewaveform states into a data stream that is input 992 to the memory ornetwork 250 in FIGS. 10 a and 10 b. The response compression control 465provides for control and selection of the waveform states, featuremeasurements and statistical measurements.

The compression methods applied by stimulus compressor 410 and responsecompressor 460, decompression methods applied by stimulus decompressor450 and response decompressor 490 and feature measurements applied bywaveform feature processor 900 are not limited to those described abovefor the preferred embodiments for stimulus and response waveforms havingwaveform states. Other algorithms or methods for compression,decompression and feature measurement can be applied without departingfrom the spirit and scope of present invention. However, it is importantthat implementations of the compression and decompression algorithms canoperate in real time so that they are effective in mitigating datatransfer bottlenecks.

The present invention can be implemented in test and measurement systemsusing a variety of technologies. Referring to FIG. 4, the stimuluscompressor 410 and response decompressor 490 can be implemented insoftware in the host computer 100. Referring to FIGS. 7 a and 7 b, thestimulus decompressor 450 can be part of a stimulus source device 710.The stimulus source device can be implemented in a test head 300 in thetest system architecture of FIG. 2 or in the test chassis 330 of in thetest system architecture of FIG. 3. Similarly, the response compressor460 of FIGS. 8 a, 8 b and 9 a and the waveform feature processor 900 ofFIGS. 9 a and 10 a can be part of a response processor 810. The responseprocessor 810 can be implemented in the test head 300 of the test systemarchitecture of FIG. 2 or in the test chassis 330 of the test systemarchitecture of FIG. 3. For these test system architectures, thestimulus decompressor 450, response compressor 460 and the waveformfeature processor 900 can be implemented in software and/or firmware inat least one of a microprocessor, microcontroller and digital signalprocessor (DSP). They can also be implemented in hardware in an fieldprogrammable gate array (FPGA), complex programmable logic device (CPLD)or application specific integrated circuit (ASIC). Referring to FIGS. 7c and 7 d, the stimulus decompressor 450 can be part of a self-testingsystem 720 in a BIST architecture. Referring to FIGS. 8 c, 8 d and 9 b,the response compressor 460 and the waveform feature processor 900 ofFIGS. 9 b and 10 b can be part of a self-testing system 820 in a BISTarchitecture. For the BIST architectures the stimulus decompressor 450,the response compressor 460 and the waveform feature processor 900 canbe implemented as parts of a testing core embedded in a SoC.

Embodiments of compression and decompression in an ASIC can beimplemented using ASIC design tools and methodologies well known tothose skilled in the art. An ASIC implementation of the compressionand/or decompression algorithms of the present invention can be designedusing a hardware description language such as VHDL or Verilog. Theregister-transfer-level (RTL) representation generated in VHDL orVerilog can then be synthesized into a gate-level representation of thealgorithms for the ASIC implementation. The hardware descriptionlanguage instructions can be stored on a CD-ROM, hard disk or othercomputer-readable medium for distribution and downloading to a processorthat will synthesize the ASIC implementation.

The compression and decompression can also be implemented in one or moreprogrammable processors. The programmable processors includesoftware/firmware programmable processors such as computers, digitalsignal processors (DSP), microprocessors (including microcontrollers)and other programmable devices, and hardware programmable devices suchas complex programmable logic devices (CPLD), field programmable gatearrays (FPGA) devices. Depending on the type of programmable processor,the program implementing the operations of the present invention isrepresented by software, firmware, netlist, bitstream or other type ofprocessor executable instructions and data.

Implementations of the present invention can perform waveform statecompression in real time, that is, at least as fast as the sample rateof the waveform samples, after the training phase. Waveform statecompression operations include threshold comparators for determiningwaveform states, accessing pattern vectors from memory and subtractors.For compression of edge state sample vectors, the first sample in theedge state sample vector is used to indicate an index for a table of theedge pattern vectors in memory. Determining the index using the firstsample or another sample of the edge state sample vector is a simpleoperation. Embodiments using Huffman encoding for level state encodingalso involve simple table look-ups. Decompression operations can also beperformed in real time. Decompression operations involve using codes inthe compressed waveform data to look up the associated pattern vectors,decoding any error and adding the decoded error to the pattern vector.Huffman decoding for the level states again involves simple tablelook-up.

While the preferred embodiments of the invention have been illustratedand described, it will be clear that the invention is not limited tothese embodiments only. Numerous modifications, changes, variations,substitutions and equivalents will be apparent to those skilled in theart, without departing from the spirit and scope of the invention, asdescribed in the claims.

1. In a test system for a device under test (DUT) that includes a hostprocessor, the host processor providing a stimulus waveform to astimulus interface coupling the host processor to an input of the DUT, adevice output interface connected to an output of the DUT and a responseinterface coupling the host processor to the device output interface, amethod for sending a response waveform to the host processor from theDUT, wherein the response waveform is generated by the DUT in responseto the stimulus waveform, the method comprising: receiving the stimuluswaveform at the input of the DUT from the stimulus interface; at thedevice output interface: receiving the response waveform from the outputof the DUT; compressing a plurality of samples of the response waveformto form compressed response waveform data; transferring the compressedresponse waveform data to the response interface; at the host processor:retrieving the compressed response waveform data from the responseinterface; and decompressing the compressed response waveform data toform a decompressed response waveform.
 2. The method of claim 1, whereinthe response waveform is an analog response waveform, the step ofreceiving the response waveform further comprising: converting theanalog response waveform to a digital form to produce the plurality ofsamples of the response waveform.
 3. The method of claim 1, wherein atleast one of the step of compressing and the step of decompressing isperformed in accordance with a control parameter.
 4. The method of claim1, wherein the step of compressing operates in one or more compressionmodes, including at least one of a lossless compression mode and a lossycompression mode.
 5. The method of claim 1, wherein the responseinterface comprises a data storage device, including but not limited toat least one of a memory and a computer-readable medium, the step oftransferring further comprising storing the compressed response waveformdata in the data storage device and the step of retrieving furthercomprising retrieving the compressed response waveform data from thedata storage device.
 6. The method of claim 1, wherein the responseinterface comprises a data transfer interface, including but not limitedto at least one of a bus, a cable and a network, the step oftransferring further comprising transferring the compressed responsewaveform data via the data transfer interface and the step of retrievingfurther comprising receiving the compressed response waveform data fromthe data transfer interface.
 7. The method of claim 1, furthercomprising: measuring a feature of at least one of the responsewaveform, the compressed response waveform data and the decompressedresponse waveform.
 8. The method of claim 1, wherein the stimuluswaveform is an analog stimulus waveform, the host processor providing aplurality of stimulus waveform samples to the stimulus interface, themethod further comprising: converting the stimulus waveform samples tothe analog stimulus waveform, wherein the analog stimulus waveform isprovided to the input for the step of receiving.
 9. In a test system fora device under test (DUT), an apparatus for transferring a responsewaveform from the DUT to a host processor in the test system, the DUThaving an input and an output, wherein the DUT responds to a stimuluswaveform received at the input to produce the response waveform at theoutput, wherein the stimulus waveform is provided by the host processor,comprising: a stimulus interface coupled to the host processor and theinput of the DUT to provide the stimulus waveform to the DUT; a deviceoutput interface coupled to receive the response waveform from theoutput of the DUT; a response compressor coupled to the device outputinterface and compressing a plurality of samples of the responsewaveform to form compressed response waveform data; a response interfacecoupled to receive the compressed response waveform data from theresponse compressor; and a response decompressor coupled to receive thecompressed response waveform data from the response interface anddecompressing the compressed response waveform data to form adecompressed response waveform provided to the host processor.
 10. Theapparatus of claim 9, wherein the response waveform is an analogresponse waveform, the device output interface further comprising: ananalog-to-digital converter coupled to receive the analog responsewaveform from the output of the DUT and converting the analog responsewaveform to a digital form to produce the plurality of samples of theresponse waveform.
 11. The apparatus of claim 9, wherein at least one ofthe response compressor and the response decompressor operates inaccordance with a control parameter.
 12. The apparatus of claim 9,wherein the response compressor operates in one or more compressionmodes, including at least one of a lossless compression mode and a lossycompression mode.
 13. The apparatus of claim 9, wherein the responseinterface comprises a data storage device, including but not limited toat least one of a memory and a computer-readable medium.
 14. Theapparatus of claim 9, wherein the response interface comprises a datatransfer interface, including but not limited to at least one of a bus,a cable and a network.
 15. The apparatus of claim 9, wherein the deviceunder test, the device output interface and the response compressor areadapted to be implemented in a self-testing system for the device undertest, wherein the self-testing system is coupled to provide thecompressed response waveform data to the response interface.
 16. Theapparatus of claim 10, wherein the device under test, the device outputinterface, including the analog-to-digital converter, and the responsecompressor are adapted to be implemented in a self-testing system forthe device under test, wherein the self-testing system is coupled toprovide the compressed response waveform data to the response interface.17. The apparatus of claim 9, wherein the stimulus waveform is an analogstimulus waveform, the host processor providing a plurality of stimuluswaveform samples to the stimulus interface, the stimulus interfacefurther comprising: a digital-to-analog converter to convert thestimulus waveform samples to the analog stimulus waveform provided tothe input of the DUT.